1. Field of the Invention
The present invention relates to a computer device and method capable of reducing a memory capacity of a read-only memory (ROM) for storing a program therein.
2. Description of the Related Art
FIG. 10 shows a conventional example of a configuration of a computer device for executing a program stored in a ROM with a 32-bit microprocessor. The ROM 3 stores an object code containing a large number of instruction words. The term "object code" herein indicates an executable form program, not a relocatable form program. Moreover, the object code includes not only a program but also normal data in some cases. The term "instruction word" herein merely refers to a code. The code is obtained by dividing the object code so as to have an arbitrary length. The instruction word includes not only an instruction code for executing a command, but can include a code of an address which is possibly appendant to the instruction code, such as a code of an address or a code of immediate data and various data codes within the object code.
A microprocessor 1 transmits an address via an address bus 4 from an address register 1a to read the instruction word stored at an address of the ROM 3. The address bus 4 is a 32-bit address bus, via which a 32-bit address is transmitted. However, it is not necessary that the ROM 3 should have an address space of 32 bits (2.sup.32) In the case where the instruction word to be read out is an instruction code for executing a command, the address transmitted from the address register 1a is an effective address. The effective address may be generated by a program counter. The program counter is located in an internal register group 1b. In the case where the instruction word to be read out is data or the like, the address transmitted from the address register 1a is an effective address obtained by converting the address stored in one of the registers other than the program counter in the internal register group 1b as needed.
The instruction word read from the ROM 3 by transmission of the address is read in the microprocessor 1 via the data bus 5, and then is temporarily held in the data register 1c. In the case where the instruction word is an instruction code, the instruction word is transmitted to an instruction decoder 1d and is decoded therein. Then, in accordance with the result of decoding, a control section (not shown) executes an operation command designated by the instruction word. For example, in the case where the instruction word designates an operation process between the registers, the data in the specified register within the internal register group 1b is processed in an arithmetic and/or logic unit (hereinafter, referred to as ALU) 1e. Then, the result of the arithmetic and/or logic process is stored in the specified register within the internal register group 1b. In the case where the instruction word is not an instruction code, the instruction word is transmitted from the data register 1c to a register within the internal register group 1b or the ALU 1e. The address register 1a, the internal register group 1b, the data register 1c and the ALU 1e are connected to each other via internal buses (not shown).
The microprocessor 1 includes a memory management unit 1f and a cache memory 1g. The memory management unit 1f converts a logic address into a physical address, and supports an exceptional process in memory protection or virtual memory of an operating system (OS). Therefore, in actuality, the address transmitted from the address register 1a is a physical address converted by the memory management unit 1f. The cache memory 1g is a semiconductor memory device operating faster than the ROM 3. The cache memory 1g collectively reads out the instruction words from the ROM 3, and successively supplies the instruction words to the microprocessor 1 in accordance with the addressing. Therefore, in actuality, the instruction words read out from the ROM 3 are transmitted to the cache memory 1g via the data bus 5, and then are supplied to the data register 1c therefrom. The microprocessor 1 does not need to perform a low-speed read-out from the ROM 3 as long as the specified address is hit in the cache memory 1g. However, hit rate is lowered if a branch instruction or the like is frequently used. In such a case, even when the cache memory is provided, the reading of the instruction word becomes complicated. Thus, even when the cache memory is provided, the program is not always executed at high speed.
In an actual computer device, even if the whole program is stored in the ROM 3, a random access memory (RAM) (not shown) serving as a work area upon execution of the program and an I/O port (not shown) for input/output of an input device or a display device are connected to each other via the address bus 4 and/or the data bus 5. The RAM and the I/O port perform the same reading and writing processes as in the ROM 3.
Since program sizes have increased to enable recent computer devices to have enhanced functions, these recent computer devices now require memory devices having large capacity. However, in a computer device, in particular, in a portable computer device, a mount area for IC or the like is limited due to the reduced size of the computer device. Furthermore, since power consumption and fabrication cost are desired to be lowered, it is not possible to infinitely increase the memory capacity of the portable computer device. As a result, the size of an application program is limited, so that the function and performance of the computer device are adversely forced to be lowered. If the optimization is performed when a compiler compiles a program, the size of an object code can be reduced. The optimization with the compiler is mainly performed for omitting unnecessary code generated by programming with a high-level language so that the program approaches a program which is optimally programmed in an assembler. However, the degree reduction in size obtainable by this optimization is limited.
In order to overcome the above disadvantages, a technique employing data compression is conventionally utilized. According to this technique, the capacity of the memory can be reduced by decreasing the size of the object code of the program or the data stored in an external memory device such as a hard disk device, or the data size stored in a main memory device.
In the case where the program or the data stored in the external memory device is subjected to data compression, the data is expanded upon loading into the main memory device. Therefore, although the capacity of the external memory device can be reduced, the memory capacity of the main memory device cannot be reduced. In the case where the compressed data is stored in the main memory device, the data to be stored therein is limited to specific data which is internally utilized by an application program. Moreover, the application program itself is not data compressed on the main memory device because a general data compression method is the combination of a run length method and a Huffman method: the run length method converts the successive same instruction words into the combination of a code representing any one of the instruction words and a code representing a length of the successive instruction words; and the Huffman method converts each instruction word into a variable length code in accordance with its occurrence frequency. Therefore, the data compression is required to be performed in a sequential manner from the head of the object code or the head of the block. Thus, in the case where the whole object code is loaded into the main memory device, it is possible to perform data expansion in a sequential manner. Moreover, with respect to the data utilized within the application program, it may be also possible to perform data compression in a sequential manner in some cases.
However, in the case where the data-compressed object code is stored in the main memory device without performing any processing, instruction words cannot be accessed one by one in a random manner since the relative positional relationship between the compressed instruction words on the address is disordered.
Japanese Laid-Open Patent Publication No. 6-168140 discloses an optimizing method of a compiler. According to this method, the size of an object code is intended to be reduced by changing an instruction scheme of a 32-bit fixed length for a reduced instruction set computer (RISC) type microprocessor into an instruction scheme of a 16-bit fixed length. Simultaneously, the object code with high efficiency using the 16-bit fixed length instruction system is intended to be reduced.
According to the method, however, the bit size itself of the instruction word is the simplified instruction scheme of RISC or the like. The computer device according to the method is substantially the same as other conventional computer devices in that each of the instruction words is read from the object code on the main memory device in the microprocessor 1 and is then decoded to be executed. Thus, the size of the actually used object code is not appropriately reduced thereby.
Furthermore, although a processing rate of the microprocessor 1 is remarkably improved, a latency upon reading of the instruction words is increased in the case where the operation rate of the main memory device or the bus cycle remain unimproved. Thus, there arises a problem that the microprocessor 1 cannot sufficiently demonstrate its performance. In order to increase the operation rate of the main memory device, an expensive memory device should be used. Even if the operation rate is increased by employing such a memory device, a switching rate of a three-status buffer connected to the data bus 5 or the like is increased. As a result, the power consumption is disadvantageously increased thereby.